| |
.7 um 12 GHz BiCMOS
Process
Features
|
|
-Twin
Well BiCMOS
|
-Gate
oxide 150 Ang.
|
|
-LOCOS
isolated - 6550 Ang.
|
-Composite
pitch: 2.16um
|
|
-2
Layer A1 0.5% Cu
|
-Drawn
Poly: 0.8um, pitch 1.6 um
|
|
-W
plugs with Ti/TiN liner
|
-Contact:0.8um
|
|
-PtSi
Schottky (Y)
|
-M1
pitch: 2.0um, M2 pitch:2.5 um
|
|
-High
Voltage MOS xtors (H)
-Isolated NMOS xtor capability (I)
|
-D1:TEOS/PTEOS/SOG/TEOS
(1500/5000/1500 Ang)
|
|
|
-D2:
TEOS/SOG/TEOS
(6500/8000 Ang)
|
| Device
Features |
|
-NMOS
Id5x5:0.43mA/um
|
HV
devices BVdss:
|
|
-PMOS
Id5x5: -0.19mA/um
|
-Iso
HVNMOS: 20V min.
|
|
-NPN
Gain: 80
|
-HVPMOS:
30V min.
|
|
-Ft
7 GHz
|
|
| CMOS
Electrical Parameters |
|
NMOS
Devices:
|
Target
|
Min
|
Max
|
Units
|
|
BVdssn
(40/0.8@1 uA)
|
|
-10
|
|
V
|
|
Vtn
(40/0.8, Vds=0.1V, Vbs=0.0V)
|
0.725
|
0.6
|
0.85
|
V
|
|
Idsatn,
(40/0.8, Vds=Vgs=5.0V)
|
16.8
|
13.6
|
20.0
|
mA
|
|
Leffn,
(40/0.8)
|
0.65
|
|
|
um
|
|
Peak
Isubn (Vds=5.0V, Vgs=2.5V)
|
-1.35
|
-2.0
|
0
|
uA/um
|
|
M-factor
|
0.43
|
0.3
|
0.6
|
V 1/2
|
|
Isolated
HVNMOS Devices:
|
Target
|
Min
|
Max
|
Units
|
|
BVdssn
(40/1.2 w/2.4 um drift region)
|
25
|
20
|
|
V
|
|
Source-Substrate
BVssn
|
30
|
26
|
|
V
|
|
Drain-Substrate
BVdsn
|
30
|
26
|
|
V
|
|
NISO-Substrate
BV
|
|
30
|
|
V
|
|
NISO-Source
BV
|
|
20
|
|
V
|
|
Vtn
(40/1.2, Vds=Vgs=5.0V)
|
0.675
|
0.55
|
0.8
|
V
|
|
Idsatn,
(40/1.2, Vds=Vgs=5.0V)
|
13.6
|
8.0
|
18.4
|
mA
|
|
Peak
Isubn
|
-1.5
|
-3.0
|
0
|
uA/um
|
|
On
Resistance (Vds=1.0 V, Vg=5v)
|
231
|
|
294
|
V
|
|
Subthrehold
leakage
(Vds=5.5V, Vgs=0V)
|
0.25
|
0
|
1.5
|
pA/um
|
|
HVPMOS
Devices:
|
Target
|
Min
|
Max
|
Units
|
|
BVdssp
(40/1.2 w/2.4 um drift region)
|
-33
|
-30
|
|
V
|
|
Source-Substrate
BVssp
|
30
|
26
|
|
V
|
|
Drain-Substrate
BVdsp
|
30
|
26
|
|
V
|
|
NISO-Source
BV
|
|
|
-10
|
V
|
|
Vtp
(40/1.2, Vds=0.1V, Vbs=0.0V)
|
-0.78
|
-0.9
|
-0.65
|
V
|
|
Idsatp,
(40/1.2, Vds=Vgs=5.0V)
|
-4.0
|
|
|
mA
|
|
On
Resistance (Vds=1.0V, Vg=5V)
|
33
|
|
42
|
K *um
|
|
Subthreshold
leakage
(Vds=5.5V, Vgs=0V)
|
1.0
|
0
|
1.5
|
pA/um
|
|
Low
Side HVNMOS Devices:
|
Target
|
Min
|
Max
|
Units
|
|
BVdssn
(40/1.2 w/2.4 um drift region)
|
25
|
20
|
|
V
|
|
Source-Substrate
BVssn
|
30
|
26
|
|
V
|
|
Drain-Substrate
BVdsn
|
30
|
26
|
|
V
|
|
NISO-Substrate
BV
|
|
30
|
|
V
|
|
NISO-Source
BV
|
|
20
|
|
V
|
|
Vtn
(40/1.2, Vds=0.1V, Vbs=0.0V)
|
0.675
|
0.55
|
0.8
|
V
|
|
Idsatn,
(40/1.2, Vds=Vgs=5.0V)
|
13.6
|
8.0
|
18.4
|
mA
|
|
Peak
Isubn
|
-1.5
|
-3.0
|
0
|
uA/um
|
|
On
Resistance (Vds=1.0 V, Vg=5V)
|
231
|
|
294
|
V
|
|
Subthreshold
leakage
(Vds=5.5V, Vgs=0V)
|
0.25
|
0
|
1.5
|
pA/um
|
| Bipolar
Electrical Parameters |
|
Nominal
Walled NPN (2.2x2.1 emitter):
|
Target
|
Min
|
Max
|
Units
|
|
Beta@Je=100uA/um2
|
80
|
60
|
100
|
-
|
|
Early
Voltage
|
25
|
19
|
30
|
V
|
|
Vbe@Je=100uA/um2
|
0.735
|
0.72
|
0.75
|
V
|
|
Bvceo
(@1 uA)
|
7.2
|
5.5
|
|
V
|
|
Peak
Ft
|
7
|
|
|
GHz
|
|
Lateral
PNP Devices:
|
Target
|
Min
|
Max
|
Units
|
|
Beta
@Je=10 uA/um2
|
40
|
20
|
60
|
-
|
|
Early
Voltage
|
-12
|
|
|
V
|
|
Vbe@Je=10uA/um
|
0.715
|
0.7
|
0.73
|
V
|
|
Bvceo
(@1
uA)
|
7
|
5.5
|
|
V
|
|
Peak
Ft
|
100
|
|
|
MHz
|
| Valid
Device List |
|
Version
1
|
Version
2
|
|
1.
NMOS transistor
|
14.
Isloated HVNMOS
|
|
2.
PMOS transistor
|
15.
Low side HVNMOS*
|
|
3.
NPN striped transistor
|
16.
High side HVNMOS*
|
|
4.
Lateral PNP transistor
|
17.
Isloated NMOS*
|
|
5.
NLDD/P+ Zener diode
|
18.
Isolated PMOS*
|
|
6.
N+/P- well diode
|
19.
HVPMOS transistor
|
|
7.
P+/N- well diode
|
20.
P- well guard ring Schottky
|
|
8.
Poly resistor
|
21.
P+ guard ring Schottky
|
|
9.
N+ resistor
|
22.
P+ in P-well high voltage resistor
|
|
10.
P+ resistor
|
23.
P- base in P-well high voltage resistor
|
|
11.
N- well resistor
|
|
|
12.
P- base resistor
|
|
|
13.
Poly to Sink capacitor
|
*New
valid devices with 30 volt qualification
|
| New
Valid Device Requirements |
|
Device
|
Parameter
|
Current
spec
|
New
spec
|
status/approach
|
|
Low
side HV NMOS
|
NISO-Sub BD
|
30v min
|
35v min
|
Change
Layout Rule "PBX enclosure of Nwell for Nwell-PBL bias >
14 volts" from 3.5 um to TBD. |
|
High
side HV PMOS
|
"
|
"
|
"
|
|
Isolated
NMOS
|
"
|
"
|
"
|
|
Isolated
PMOS
|
"
|
"
|
"
|
|
Device
|
Parameter
|
Current
spec
|
New
spec
|
status/approach
|
|
Low
side HV NMOS
|
BV dss
|
25v min
|
35v min
|
Change
Layout Rule "PBX enclosure of Nwell on sides facing source"
from 1.5 um to 0.0 um or -0.5 um.
|
|
High
side HV PMOS
|
"
|
30v min
|
30v min
|
|
Isolated
NMOS
|
"
|
10v min
|
10v min
|
|
Isolated
PMOS
|
"
|
10v min
|
10v min
|
|
|
